Dartmouth Events

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Meeting ID: 933 9058 7164
Passcode: 210715

Contemporary microprocessor design is facing tremendous challenges in memory bandwidth and power consumption. In-memory computing (IMC) helps relieve some issues, achieving massively parallel computing with high storage density. On the other hand, its scaling trend is still lagging behind the ever-increasing demand of AI algorithms and high-definition sensors. More disruptive innovations, such as heterogeneous integration, will be critical to scaling up the system and speeding up the computation. 

In this talk, we will first review the fundamental limitations of current IMC system: device variations, peripheral circuits, and interconnection. They interact with each other, limiting the accuracy, scalability, and energy efficiency of the system. Then we will present heterogeneous solutions crossing device/circuit/architecture, based on statistical data from a fully integrated 65nm CMOS/RRAM test chip. At the circuit level, we design a hybrid RRAM/SRAM macro to fully recover the accuracy loss, employing sparse training on silicon; at the architecture level, we propose big-little IMC chiplets to maximize the utilization and minimize energy consumption. 

To efficiently explore the design space, we further develop a new benchmark simulator, SIAM, for the heterogenous IMC system, which models device/circuit/architecture, network-on-chip (NoC), network-on-package (NoP) and DRAM access to address the challenges in 2.5D/3D integration. We will conclude this talk with brainstorming on the potential and research need of such a design paradigm shift.